XmartLink™ 3D Optical Engine

RVi focuses on developing XmartLink™ 3D-packaged optical engines for CPO/NPO modules.

AI Interconnect Challenge & CPO Necessity

As AI workloads scale, conventional copper interconnects are hitting a "Cable Wall". Higher data rates increase insertion loss and heat. Co-packaged optics (CPO) bring optical I/O closer to the ASIC, reducing the electrical path length and improving bandwidth density.

OIF-3.2T-CPO Standard & Serviceability

Aligning with the OIF 3.2Tb/s CPO implementation agreement,  XmartLink™ provides standardized electrical and optical interfaces. This replaceable module architecture reduces maintenance complexity and downtime, supporting multi-module integration around high-capacity switches.

Application Scenarios

Scenario 1: Scale-Up Network (UALink)

Eliminates the "Cable Wall" by replacing copper with   XmartLink™ optical engines for GPU-to-GPU connections.

Scenario 2: Optical I/O (CXL/PCIe)

Disaggregated architecture using   XmartLink™ for high-bandwidth, low-latency Optical I/O (OIO) connecting compute nodes to distributed memory pools and peripherals.

Scenario 3: Optical Chiplet (OIO, UCIe)

Optical interconnects between chiplets via the UCIe standard interface, increasing aggregated bandwidth and transmission distance, overcoming the area density limitations and signal attenuation bottlenecks inherent in conventional copper-based packaging.

Technology Roadmap: 3D-Packaged Optical Engine

  XmartLink™ uses a 3D vertical stacking concept to integrate micro-optical elements, shrinking the footprint and pushing the optical interconnect closer to the compute die for maximum signal integrity.

Gen 1:   XmartLink™ on Substrate

Mounted on main substrate using standard BGA/Copper pillars.

Gen 2:   XmartLink™ on Interposer

Engine moves onto interposer. Shorter electrical path; 1–2 Tbps per module.

Gen 3:   XmartLink™ on SoC (3D)

True 3D integration. Directly stacked on SoC via hybrid bonding.