High-Speed Micro-VCSEL Arrays
RVi focuses on its core capabilities in highly integrated, scalable, high-speed Micro-VCSEL arrays to address the AI data center demand for higher bandwidth density, lower power, and improved serviceability.
Types of Inter-Chip Connection Technologies
While competing technologies push to extremes—either using power-hungry DSPs for Extreme Fast lanes, or complex gearboxes for Extreme Wide lanes—RVi targets the optimized Fast and Wide approach. By utilizing Micro-VCSELs (32G-112G per lane), we eliminate DSPs, achieving massive bandwidth at < 2 pJ/bit.
Architecture Specifications
|
Specification |
Extreme Fast |
Fast and Wide (RVi) |
Extreme Wide |
|---|---|---|---|
|
Per Lane Speed |
200G → 400G |
32G → 112G |
2G → 4G |
|
Optics |
Traditional SiPh (MRM, MZM) |
Micro-VCSEL |
MicroLED |
|
No. of Channels (3.2T) |
8 - 16 |
32 - 100 |
800 - 1600 |
|
Architecture Challenge |
Heavy SerDes & DSP |
Signal Optimization (No DSP) |
Gearbox, Multicore Fiber |
|
Optimal Range |
< 2km |
< 100m |
< 10m |
|
Power Eff. (Inc. SerDes) |
< 7 pJ/bit |
< 2 pJ/bit |
< 3 pJ/bit |
RVi XmartLink™ vs. Traditional SiPh Solutions
Unlike conventional Silicon Photonics approaches (like COUPE) that rely on external lasers and strict active alignment, our integrated Micro-VCSEL uses passive alignment, significantly lowering test costs and improving power per bit.
|
Feature |
RVi XmartLink™ (Micro-VCSEL) |
Traditional SiPh (Grating Coupling) |
|---|---|---|
|
Light Source |
Integrated (No External) |
External Laser Source Required |
|
Optical Efficiency |
Very High (Direct Mod.) |
Very Low (Waveguide Coupling) |
|
Alignment Tolerance |
Passive Align (± 2µm) |
Active Align (± 0.5µm) |
|
Power Per Bit |
< 1.5 pJ/bit |
~ 5.0 pJ/bit |